PIXEL STRUCTURE WITH HIGH DYNAMIC RANGE.

专利摘要:

公开号:BE1019800A4
申请号:E2012/0059
申请日:2012-01-31
公开日:2012-12-04
发明作者:Jan Bogaerts
申请人:Cmosis Nv；
IPC主号:

专利说明:

PIXEL STRUCTURE WITH HIGH DYNAMIC RANGE OF THE INVENTION
This invention relates to pixel structures and pixel matrices used in applications such as image sensors.
BACKGROUND OF THE INVENTION
A pixel structure consists of a light-sensitive element that responds to light. This light-sensitive element can be a pinned photodiode (PFD). Figure 1 shows a diagram of a four transistor (4T) pixel structure with a pinned photo diode. The pixel is controlled by reset, transfer and row selection switches. The photosensitive element generates photo charge in response to light. For reading the photo charge, the floating diffusion (FD) is reset by the reset switch. The reset level is read by the source follower and the selection transistor to the bus column. Then, the charge collected on the photodiode is transferred by the transfer transistor to the floating diffusion FD. This signal level is re-read by the source follower and the selection transistor.
An advantage of the pinned photodiode is that photo charge is collected during the integration time and that the charge can then be transferred to the floating diffusion during the pixel reading. This makes it possible to use a read-out technique called correlated double sampling (CDS) which eliminates kTC reset noise from the floating diffusion. In addition, the pinned photodiode results in a low dark current because the charge packet is shielded from the surface.
However, pinned photo diodes have some drawbacks. A disadvantage of the pinned photodiode is that the dynamic range is more limited compared to a conventional photodiode, such as an n-well / p-substrate junction in a three transistor (3T) pixel. The dynamic range is the range, typically expressed in a ratio, between the largest intensity value that can be read out by the pixel, and the smallest intensity value that can be read out from the pixel. This disadvantage is particularly problematic if the pixel size is reduced.
An article “4.5pm Pixel Pitch 154 ke Full Well Capacity CMOS Image Sensor” and US patent application US 2008 / 0237446A1 describe a pixel that looks like a 4T PPD pixel, but with an added overflow capacity, called a “Lateral Overflow Integration Capacitor (LOFIC ), And a switch that connects the LOFIC to the floating diffusion. A large signal causes an overflow of charge from the photodiode to the overflow capacity during the integration.
The present invention provides an alternative way to increase the dynamic range of the pixel structure.
SUMMARY OF THE INVENTION
An aspect of the invention consists of a pixel structure with a photosensitive element to generate charge in response to light and a charge conversion element. A first transfer rate is connected between the photosensitive element and the charge conversion element. A charge storage element is connected to the photosensitive element. The charge storage element has a higher charge density than the photosensitive element. The charge storage element is disposed on the photosensitive element side and is provided to collect charge that is generated in the photosensitive element during an integration time.
Charge (photo charge) is generated in response to light during an integration time. The charge storage element provides an additional charge storage area for the charge, thereby extending the ability of the pixel to read out a larger signal, thereby increasing the dynamic range. Collecting the generated charge on the photosensitive element allows good pixel performance in various modes of use, such as a rolling shutter operation mode, and a global shutter operation mode. Charge stored on the charge storage element is read out after the integration time. This charge storage element contributes to a signal value that is read from the pixel.
Advantageously, the charge storage element has a charge density which is at least twice the charge density of the photosensitive element. More advantageously, the charge density of the charge storage element is five times the charge density of the photosensitive element. Even more advantageously, the charge density of the charge storage element is at least ten times the charge density of the photosensitive element.
In some pixel structures, the photosensitive element is used as a charge storage element. However, the charge storage element should not be light sensitive because there is no need for direct collection of optically generated charges by this element. Typically, the charge storage element receives charge from the photosensitive element (e.g. PPD) if necessary because of the limited charge storage capability of the photosensitive element (e.g. PPD). Advantageously, the largest area of the pixel is used for the photosensitive element (e.g. PPD) and a smaller portion of the pixel is used for the charge storage element to achieve the required dynamic range.
Advantageously, the pixel structure further comprises a control for controlling the operation of the pixel structure. This control is configured to cause the pixel structure charge to collect in at least one photosensitive element and the charge storage element during the integration time. The controller is further configured to transfer charge to the charge conversion element via the first transfer gate at the end of the integration time.
Advantageously, the controller is configured to transfer the pixel structure charge collected on the charge storage element to the charge conversion element via the photosensitive element and the first transfer gate at the end of the integration time.
Improvements offered by implementations of this invention are particularly advantageous for small pixel structures.
BRIEF DESCRIPTION OF THE DRAWINGS
Implementations of the invention are described by way of example only, with reference to the accompanying drawings in which:
Figure 1 shows a conventional four transistor (4T) pixel with a pinned photo diode; "c
Figures 2A-2C show a front end of a pixel structure with a pinned photo diode and a photo gate according to an implementation of the present invention and a sequence of potential diagrams during the operation of the pixel;
Figure 3 shows a conventional pixel with a photo gate.
Figures 4A-4C show a front end of a pixel structure that uses a pinned photo diode and a photo gate according to an implementation of the present invention and a sequence of potential diagrams during the operation of the pixel;
Figures 5A and 5B show a front end of a pixel structure that uses a pinned diode, a lateral overflow barrier and a photo gate according to an implementation of the present invention and a sequence of potential diagrams during the pixel operation;
Figures 6A and 6B show a front end of a pixel structure that uses a pinned diode, a lateral overflow barrier, and a capacitance according to an implementation of the present invention and a sequence of potential diagrams during the pixel operation;
Figures 7A and 7B show a front end of a pixel structure using a pinned photodiode, a transfer gate and a photo gate according to an implementation of the present invention and a sequence of potential diagrams during the "operation of the" pixel;
Figures 8A and 8B show a front end of a pixel structure using a pinned photodiode, a transfer gate and a capacitance according to an implementation of the present invention and a sequence of potential diagrams during the pixel operation;
Figures 9A to 9F show pixel structures capable of working with a global shutter;
Figures 10 and 11 show timing diagrams for Figures 9A to 9B
Figure 12 shows schematically a pixel array architecture
DESCRIPTION OF PREFERENTIAL IMPLEMENTATIONS OF THE INVENTION
The present invention will be described by specific implementations and with reference to specific drawings, but the invention is not limited to these but only to the claims. The described drawings are only schematic and not limitative. The size of some elements in the drawings can be exaggerated and for illustrative purposes the drawings are not drawn to scale. When the word "comprising" is used in the present description and claims, it does not exclude other elements or steps. Furthermore, the words first, second, third and the like in the description and the claims are used to distinguish between similar elements and not necessarily for the description of a sequential or chronological order. It is to be understood that these terms so used are interchangeable under suitable conditions and that the implementations of the invention described herein are capable of operating in sequences other than those described or illustrated in this text.
The words "horizontal" or "vertical" are used in this text to distinguish between two orthogonal directions and do not impose a specific orientation of the matrix.
Different implementations will now be described.
PPD combined with PG
A pinned photo diode (PPD) is combined with a photo gate (PG). Pixel structures are shown in Figures 2A and 2B. A sequence of potential diagrams during the pixel operation is shown in Figure 2C. The combination shown in Figure 2A or 2B is used in place of combination 10 of the PPD and the transfer gate as shown in Figure 1. Figure 2A shows one of the simplest topologies for the pixel readout portion. The readout portion of the pixel can be made with many different topologies and is not limited to that shown in Figure 2A.
As background information, Figure 3 shows a conventional scheme of a pixel with a photo gate PG. During the integration time, charge is collected under the photodiode (similar to charge collection in the PPD). Charge becomes. transferred during reading to the FD. Like in a PPD pixel, the kTC becomes
reset noise eliminated by CDS. Since the gate forms a MOS capacity and can be controlled to higher voltages, the charge storage is higher than with the PPD. Disadvantages of the PG structure are that it partially absorbs the light (especially for short wavelengths) and that the dark current is typically worse than with the PPD. For a full charge transfer, the PG / TX required a very small distance between both gates that is not possible in standard CMOS processing. It therefore requires an adapted process to avoid potential barriers or valleys and charge transfer problems. Because of these disadvantages, this pixel structure is rarely used today and the PPD structure is preferred.
Figure 2C shows a sequence of potential diagrams during the operation of the pixel. In each potential diagram, higher potential is shown in the downward direction of the diagram. An operating cycle of the pixel comprises the following steps (phases): reset, integration (also called exposure) and transfer. The terms "exposure" and "integration" are interchangeable throughout this description. The photo gate was driven low during the reset and transfer phases. During integration, the photo gate signal is high and photo charges are collected both under the photo gate (for low and high signal levels) and the PPD (for high signal levels). During the transfer phase, the charge under the PG and PPD is fully transferred to the FD. Figure 2C shows the integration phase for a small signal (i.e. at a low light level) and a large signal (i.e. at a high light level). In Figure 2C, a small signal is only stored in the PG. A large signal is stored both under the PG and the PPD.
Figure 2C shows a higher potential below the PG compared to the PPD.
If the potential under the PG is lower than under the PPD, the effect will be reversed. A small signal is then stored only under the PPD and a large signal is stored under a combination of the PPD and the PG.
Charge is not transferred to the FD until the transfer gate is turned on. This configuration combines the good features of the PPD and the PG without inheriting most of its disadvantages. The PG provides a higher charge density without the requirement to make the gates with very short spacing (as required in the pixel with only a PG as in Figure 3) and without the reduction of the sensitivity to short wavelengths. To explain the problem of the small distance between adjacent gates, we refer back to the pixel with only PG of Figure 3. The PG and TX gates are next to each other to obtain a good charge transfer from charge under the PG to the TX (such as in a CCD). This requires non-standard CMOS processing. In such a case, it must be ensured that there is no barrier between the gates, or that no valley is created (where charge can be trapped) and that there is a sufficient electric field from the neighboring gates during the transfer to allow charge transfer. speed up. In Figures 2A-2C, the TX gate is not immediately adjacent to the PG but adjacent to the PPD as in a single PPD pixel. Load under the PG is transferred to the PPD without the need for adjacent gates.
The PG can be designed in a small fraction of the pixel surface to achieve the saturation charge (FWC) specification. This limits its contribution to dark current while maintaining a good MTF (modulation transfer function) due to the PPD.
The term "pinned" in "pinned photodiode" means that the surface potential of the photodiode is pinned to the substrate potential (because the p + implantation on the surface of the photodiode is connected to the substrate). More generally, this term means that such a diode can also be completely depleted. When charge is transferred, the photodiode is completely free of minority charge carriers. At this time, her potential is also "pinned" to a maximum voltage Vpin.
With respect to charge density, a pinned diode (PPD) typically has a density of 1 to 5 Ke / pm 2 (1000 to 5000 electrons per square micrometer). A gate capacity is typically in the order of a few fF / pm 2 (typically 5-7 fF / pm 2). 1 fF can store 6250 electrons over a signal of IV, which means that a gate capacity of 5-7 fF / pm can store a charge of more than 30 Ke / pm over 1 Volt. Other values for. load density are possible in the PPD and PG. The charge density in the charge storage element can be at least five times higher than the charge density in the photosensitive element, and can be an order of magnitude greater than the charge density in the photosensitive element.
PPD combined with PD
A pinned photo diode (PPD) is combined with a photo diode (PD). The photodiode can be a second pinned photodiode that is not completely depletable. Pixel structures are shown in Figures 4A and 4B. A sequence of potential diagrams during the operation of the pixel is shown in Figure 4C. The combination shown in Figure 4A or 4B is used in place of the combination 10 of the pinned photo diode as shown in Figure 1.
Referring to Figure 4C, the photo diode is reset through the PPD during the reset and transfer phases. Loads stored in the PPD are fully transferred to the FD. During integration, the charge is collected in both the PD and the PPD (for high and low signal levels). This combination has a similar advantage as the PPD combined with PG, but is simpler in design and requires no extra control line. Resetting the PD through the PPD can cause image lag ("image lag") and the associated noise. However, this remains lower than in a 3T pixel. The image trailing can also be eliminated by a hard or soft reset of the PD by checking through the FD voltage.
PPD combined with a lateral overflow barrier (LOB) and PG
A pinned photodiode (PPD) is combined with a lateral overflow barrier and a PG. The pixel structure is shown in Figure 5A. A sequence of potential diagrams during the operation of the pixel is shown in Figure 5B. The combination shown in Figure 5A is used instead of the PPD combination and the transfer gate shown in Figure 1. A constant-voltage hole can be used in place of the LOB and has a similar effect to the LOB.
The lateral overflow barrier (LOB) is an area with a fixed potential. During the reset or transfer phase, the PG (low pulsed) is reset by the PPD. Load stored in the PG and the PPD is fully transferred to the FD. During integration, the PG is pulsed high and the photo charge is collected in the PPD (for small signals) and in the PG (for high signals). The combination again brings similar advantages as the PPD combined with PG, but the additional advantage that for small signals the photo charge is only collected in the PPD. In case when the photo charge is read sequentially (with a first transfer without pulsing PG layer), only the charge collected in the PPD is transferred. Only dark current from the PPD is added to this signal. For large signals (after pulsing PG low), both dark current from the PPD and from the PG are added.
A gate with a constant voltage (DC) can be used instead of (the LOB. A DC gate is a transfer gate with the control voltage of the gate connected to a constant DC signal. This creates an area with a fixed potential.
PPD combined with a lateral overflow barrier (LOB) and a capacity
A pinned photodiode (PPD) is combined with a lateral overflow barrier (LOB) and a capacitance C0verfiow. The pixel structure is shown in Figure 6A. A sequence of potential diagrams during the operation of the pixel is shown in Figure 6B. The combination shown in Figure 6A is used instead of the PPD and Transfer Gate combination as shown in Figure 1. A constant-voltage gate can be used in place of the LOB and has a similar effect to the LOB.
The capacitance can be made by various types but must support a pulsed operation (with a first terminal connected to the junction adjacent to the LOB, and a second terminal connected to a control signal being pulsed). The lateral overflow barrier is an area with a constant potential. During reset or transfer phases, the second terminal of the capacity is highly pulsed. Load stored on the PPD is fully transferred to the FD, the load in the overflow capacity is partially transferred. During integration, the second terminal of the capacity is pulsed low and the load is stored in the PPD (for small signals) and in COVerfiow (for large signals). The combination is similar to the combination of PPD and LOB and PG, but does not have the option of a full charge transfer. The capacity can be realized, for example, as a Metal-insulator-metal (MiM or MoM) capacity, Poly-insulator-poly (PiP) or an MOS capacity (which is more general than a PG).
PPD combined with transfer gâte (TX) and PG
A pinned photo diode (PPD) is combined with a second transfer gate (TX2) and a photo gate (PG). The pixel structure is shown in Figure 7À. A sequence of potential diagrams during the operation of the pixel is shown in Figure 7B. The combination shown in Figure 7A is used in place of the combination 10 of the PPD and transfer gate shown in Figure 1. Unlike the lateral overflow capacity in the PPD + LOB + PG and PPD + LOB + CAP, let the second transfer gate TX2 to change the potential for overflow or readout of charge from or to the photogate PG. During the reset and transfer phases, the PG layer is pulsed while TX2 is relatively low. Load stored in the PPD and PG is fully transferred to FD. During integration, the PG is pulsed high (with TX2 low) and photo charge is collected in the PPD (for small signals) and in the PG (for large signals). The combination is similar to PPD + LOB + PG and has the same advantages, but makes it possible to collect more cargo in the PPD since the overflow capacity can be changed. A disadvantage is that two adjacent gates are required.
PPD combined with transfer gate (TX) and capacity (CAP)
A pinned photo diode (PPD) is combined with a second transfer gate (TX2) and an overflow capacity C0verfiow. The pixel structure is shown in Figure 8A. A sequence of potential diagrams during the operation of the pixels is shown in Figure 8B. The combination shown in Figure 8A is used in place of the combination 10 of the PPD and transfer gate as shown in Figure 1.
The capacity can be made by different types. It should not support a pulsed operation, although a pulsed operation can be considered. The capacity can be made, for example, by a Metal-Insulator-Metal (MiM or MoM), Poly-Insulator-Poly (PiP), or MOS capacity.
In addition, the capacity can be made as a junction capacity (of the PD for example). This is the case because the potential of the TX2 gate can be changed in this case, while it could not be changed in the case of PPD + LOB + Cap in which the LOB potential was fixed. The potential difference allows charge to overflow, so that only the potential in the transfer area or storage area (by pulses from one side of the capacitance) must be changed between integration cycle and reset / transfer cycle (or both potentials).
In contrast to the case for the lateral overflow barrier in PPD + LOB + PG and PPD + LOB + CAP, the second transfer hole TX2 allows to change the potential for overflow or readout of charge from / to PG. During reset or transfer phase the TX2 signal is high (it can be pulsed low again to end transfer / reset). Charge stored in the PPD is fully transferred to the FD, charge in the capacity only partially. During integration, TX2 is low (higher than TX1) and the photo charge is collected in PPD (for small signal levels) and in the overflow capacity (for large signal levels). The combination is similar to PPD + TX + PG and has the same advantages. An advantage is that two adjacent gates are not required, but a disadvantage is that the charge transfer of the overflow capacity COVerflow is not complete (see also PPD + PD).
HDR pixels with rolling shutter
The pixel structures described above can be used with pixels with a rolling shutter (curtain shutter).
HDR pixels with global shutter
The pixel structures described above can be used with global shutters. Figures 9A-9F schematically show pixels capable of operating with a global shutter. In each of these cases, one of the previously described configurations forms the light-receiving portion of the pixel. A complete description of the topology and operation of a global shutter pixel is described in European patent application EP 2 109 306 A2.
In Figures 9A and 9C, overflow capacity C0Verfiow is reset to Vpin. Vpin is the potential when PPD is empty. Due to design and processing, the potential cannot become higher in the PPD due to the complete depletion of the diode. Coverfiow cannot be fully depleted and is never "empty". It always contains charge depending on the externally applied voltage. During the reset phase, the gray area represents charge that fills the capacity up to the level determined by Vpin (because the reset happens through the PPD) after reset. Capacity C1 stores the reset level of the pixel. Capacity C2 stores the signal level of the pixel after the charge transfer to Cfd.
In Figs. 9B, 9D and 9E, the photo gate PG is, ideally, completely empty (due to a low voltage on the gate). If not, the channel potential is the same as Vpin in the photodiode.
The transfer gate TX2 is the overflow gate. This can be pulsed during the Frame Overhead time (FOT) in Figure 9A. FOT is a term typically used in sensors with a global shutter and is the period during image reading during which the sequence of global pulses is performed on the pixels. The pixels are read after the FOT.
In Figure 9E and Figure 9F, charge is immediately integrated on the photogate / n-well photodiode (with a higher charge density than the pinned diode). This can result in a higher dark current or readout noise.
The photo gate PG in Figure 9E may, alternatively, be a second transfer gate. It is the charge storage function of this gate that is used.
Figure 10 is an example of the FOT timing sequence. Figure 11 is an example of the single row readout sequence.
During the frame overhead time (FOT), the FD is first made floating by switching off the reset transistor. The reset noise is therefore saved on the current diffusion. Meanwhile, both sample_1 and sample_2 switches are turned on and the reset level is sampled on both C1 and C2. After sampling, sample_2 is turned off and the reset level is saved at C2. Then the photo-generated charge is transferred from the pinned photodiode to the floating diffusion by turning on the TX transistor. Meanwhile, because sample_l is still on during the transfer process, the light signal that is being converted to FD will also be sampled to Cl. After sampling, the sample_l switch switches off so that the light signal is stored on Cl. The pixel is ready for the start of the integration of the next image. During integration, the FD remains in a reset state and the transfer gate serves as a drain for large signals in the case of saturation (anti-blooming drain).
During the row overhead time (ROT), the SEL transistor is turned on so that the reset level stored on C2 is read out first. Then sample_2 is switched on so that C1 and C2 are shorted. The photo signal stored on C1 is hereby weakened by a factor of 2 if C1 and C2 have an equal capacity. After this, this weakened signal is read out as the light signal. Two operating modes can be realized during this process. If sample_2 is switched off before the end of the SEL pulse, C2 causes a full switching cycle of the sample_2 transistor. If sample_2 is not disabled when the photo signal is read on Cl, then the kTC is noise from the. sample_2 transistor not included in the light signal, resulting in a lower readout noise for the pixel (although an additional offset is introduced).
Figure 12 shows an architecture of a pixel matrix and associated circuits. A pixel matrix 30 contains a matrix of individual pixels 31 which can be placed as a 1D or 2D matrix. Each pixel 31 can be of the type of one of the pixels shown in one of the preceding figures, or a variant of these. Typically there is an output bus per line of pixels (typically per column) in the matrix 30 on which the pixel signal values are selectively output. Output circuit 45 processes signal values 32 output from each pixel 31 of the matrix 30. Each pixel can output a single value or multiple signal values. If double sampling or correlated double sampling (CDS) is performed, values representative of reset noise are output 32. The output circuit 45 shown in Figure 45 can be divided by all outputs of the pixel matrix 30 on a time-multiplexed basis. An alternative is to provide an output circuit 45 per column, or per another line of the matrix 30, to increase data throughput.
Driving circuit 40 controls the operation of the pixel matrix 30 and output circuits 45. Driving circuit 40 includes row selection and line driving circuits to generate control signals on control lines 42 to control pixels 31 in the matrix 30. Drive circuit 40 checks: resetting the pixels to check the integration time; operation of the transfer gates TX1, TX2 to transfer charge to the floating diffusion (or multiple floating diffusions); operation of the switch reset, select, sample_1, sample_2, to check the reading of a pixel. Examples of timing schemes for the control signals are shown in Figures 10 and 11. The pixel matrix can be read in a conventional manner, with pixels scanned row by row. Drive circuit 40 can perform a global shutter function by synchronous operation of the control signals that control the respective integration time in all pixels of the matrix. The logic of driver circuit 40 may be stored in a hard-coded form, such as in a circuit, or it may be stored in a form of reconfigurable device, such as a logical array (programmable or reconfigured array) or a processor that executes software. All elements shown in Figure 12 can be provided on a single semiconductor circuit or the elements can be scattered over different circuits.
The invention is not limited to the implementations described in this text, which can be changed or varied without departing from the intention of the invention.

权利要求:
Claims (18)
[1]
A pixel structure comprising: a photosensitive element that generates charge in response to light; a charge conversion element; a first transfer gate connected between it. photosensitive element and the drawer conversion element; a charge storage element connected to the photosensitive element, with a higher charge density on the charge storage element than; on the photosensitive element; wherein the charge storage element is placed on the photosensitive element side and is configured to collect charge generated by the photosensitive element during an integration time.
[2]
A pixel structure according to claim 1, wherein a charge density of the charge storage element is at least twice a charge density on the photosensitive element.
[3]
A pixel structure according to claim (1) wherein a charge density of the charge storage element is at least five times a charge density on the photosensitive element.
[4]
A pixel structure according to claim (1) wherein a charge density of the charge storage element is at least ten times a charge density on the photosensitive element.
[5]
A pixel structure according to claim (1) wherein the photosensitive element is a pinned photo diode.
[6]
A pixel structure according to claim (1) wherein the photosensitive element is connected to the charge storage element without an intermediate potential barrier such that, in use, charge is collected over a combination of the charge storage element and the photosensitive element.
[7]
A pixel structure according to claim (1), further comprising a potential barrier between the photosensitive element and the charge storage element such that, in use, charge is first collected by the photosensitive element and, when the barrier is reached, charge overflows and is collected by the load storage element.
[8]
A pixel structure according to claim (7) wherein the barrier is a barrier with a fixed potential.
[9]
A pixel structure according to claim (8), wherein the barrier is formed by either a lateral overflow barrier or a constant-voltage gate.
[10]
A pixel structure according to claim (7) wherein the barrier between the photosensitive element and the charge storage element is controllable.
[11]
A pixel structure according to claim (10) wherein the controllable bamere is a second transfer gate.
[12]
A pixel structure according to claim (1) further comprising a driver circuit for a controlled operation of the pixel structure, wherein the driver circuit is configured to collect in the pixel structure: charge on at least one of the photosensitive elements and the charge storage element during a integration period; transfer charge to the charge conversion element via the first transfer gate at the end of the integration period.
[13]
A pixel structure according to claim (12) wherein the driver circuit is configured to transfer charge collected on the charge storage element to the charge conversion element via the photosensitive element and the first transfer gate at the end of the integration period.
[14]
A pixel structure according to claim (1) wherein the charge storage capacity of the charge storage element is greater than that of the photosensitive element.
[15]
A pixel structure according to claim (1) wherein the charge storage element is either a photo gate, a photo diode or a capacitance.
[16]
A pixel matrix comprising a plurality of pixel structures according to claim (1).
[17]
A method of using a pixel structure comprising a photosensitive element to generate charge in response to light, a charge conversion element, a first transfer gate connected between the photosensitive element and a charge conversion element, a first transfer gate connected between the photosensitive element and the charge conversion element and a charge storage element connected to the photosensitive element, this method comprising: generating charge in the photosensitive element in response to incident light; collecting charge on either the photosensitive element or the charge storage element or both elements during an integration period, wherein the charge storage element has a greater charge density than the photosensitive element; . transferring charge to the charge conversion element via the first transfer gate at the end of the integration period
[18]
A method according to claim (17) further comprising transferring charge collected on the charge storage element to the charge conversion element via the photosensitive element and the first transfer gate at the end of the integration period.

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法律状态:

优先权:

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申请号 | 申请日 | 专利标题

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GB201101742|2011-02-01|

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GB201101742A|GB2487740A|2011-02-01|2011-02-01|High Dynamic Range Pixel Structure|

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